1. Field of the Invention
The present invention relates to a switching output circuit.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a conventional switching circuit which is applied to TTL. An input terminal IN is connected to the base of an NPN transistor Q.sub.4. The NPN transistor Q.sub.4 has an emitter which is connected to the ground level GND through a resistor R.sub.1 and a collector which is connected to an end of a current supply means I.sub.C. Another end of the current supply means I.sub.C is connected to a voltage source V.sub.CC for supplying power to this circuit. An NPN transistor Q.sub.5 has a base which is connected to the collector of the NPN transistor Q.sub.4, a collector which is connected to the voltage source V.sub.CC and an emitter which is connected to the ground level GND through a resistor R.sub.2. An NPN transistor Q.sub.6 has a base which is connected to the emitter of the NPN transistor Q.sub.5 and a collector which is connected to the voltage source V.sub.CC. An NPN transistor Q.sub.7 has a base which is connected to the emitter of the NPN transistor Q.sub.4 and an emitter which is connected to the ground level GND. The emitter of the NPN transistor Q.sub.6 and the collector of the NPN transistor Q.sub.7 are commonly connected to an output terminal OUT.
The operation of this circuit is now described. When voltage V.sub.BE(OFF) (voltage across base and emitter for bringing the NPN transistor Q.sub.4 into an OFF state) is applied to the input terminal IN, the NPN transistors Q.sub.4 and Q.sub.7 enter OFF states and the NPN transistors Q.sub.5 and Q.sub.6 enter ON states while the level of the output terminal OUT goes high level.
When voltage V.sub.BE(ON) (voltage across base and emitter for bringing the NPN transistor Q.sub.4 into an ON state) is applied to the input terminal IN, on the other hand, the NPN transistors Q.sub.4 and Q.sub.7 enter ON states and the NPN transistors Q.sub.5 and Q.sub.6 enter OFF states while the level of the output terminal OUT goes low level.
FIG. 2 is a timing chart showing waveforms of voltage at the input terminal IN, ON/OFF states of the NPN transistors Q.sub.7 and Q.sub.6 and through current I.sub.S flowing from the voltage source V.sub.CC the ground level GND through the NPN transistors Q.sub.6 and Q.sub.7 in the case of alternately applying the voltage V.sub.BE(ON) and the voltage V.sub.BE(OFF) to the input terminal IN.
When the voltage applied to the input terminal IN is changed from V.sub.BE(OFF) to V.sub.BE(ON), the NPN transistor Q.sub.7 is converted from an OFF state to an ON state while the NPN transistor Q.sub.6 is converted from an ON state to an OFF state. When a general transistor is converted from an ON state to an OFF state, a delay time is caused due to charges stored in its base. The resistors R.sub.1 and R.sub.2 are added in order to discharge such base storage charges. Power consumption is increased when the resistance values of the resistors R.sub.1 and R.sub.2 are reduced, while delay times are increased when the resistance values are increased.
Referring to the timing chart shown in FIG. 2, the NPN transistor Q.sub.6 enters a conducting state for a while due to such a delay time after the voltage at the input terminal IN is changed from V.sub.BE(OFF) to V.sub.BE(ON). The through current I.sub.S flows from the voltage source V.sub.CC to the ground level GND through the NPN transistors Q.sub.6 and Q.sub.7. Similarly, the NPN transistor Q.sub.7 enters a conducting state for a while after the applied voltage to the input terminal IN is changed from V.sub.BE(ON) to V.sub.BE(OFF), and the through current I.sub.S flows. The through current I.sub.S is further increased in proportion to the number of switching times when high-speed operation is performed.
In the conventional switching output circuit having the aforementioned structure, power consumption is increased by the through current I.sub.S and further increased in high-speed operation.